analog research
Analog research groups university
Georgia Tech Analog Consortium ; ece.gatech.edu/research/GTAC/
Caltech High-Speed ICs ; chic.caltech.edu/
Berkeley Wireless Research
Center ; bwrc.eecs.berkeley.edu
Iowa State ; vlsi.ece.iastate.edu
Stanford VLSI Research Group ; mos.stanford.edu
Stanford Integrated Circuits Laboratory cis.stanford.edu
Stanford Concurrent VLSI Architecture ;cva.stanford.edu
Stanford SMIrC Laboratory; smirc.stanford.edu
Berkeley Jan M. Rabaey ;bwrc.eecs.berkeley.edu
Berkeley Wireless Research Center (http://bwrc.eecs.berkeley.edu)
Stanford Microwave Integrated Circuits Laboratory (http://www-smirc.stanford.edu)
AsadAbidi Research Group(UCLA http://www.icsl.ucla.edu)
Behzad Razavi Research Group (UCLA http://www.ee.ucla.edu/faculty/bios/razavi.htm)
Georgia Tech Analog Consortium (GTAC http://www.ece.gatech.edu/research/GTAC/)
Caltech High-speed Integrated Communications Group http://chic.caltech.edu
Texas AM University (http://amsc.tamu.edu )
UCLA Research Centers; ee.ucla.edu
UCLA Asad Abidi’s Group; icsl.ucla.edu
UCLA Razavi’s CCLab ; ee.ucla.edu/~razavi/
UC Davis Electronic Circuits Research; ece.ucdavis.edu
Columbia Integrated Systems Laboratory ; cisl.columbia.edu/
University of Toronto Electronics Group; eecg.utoronto.ca
WPI Microelectronics Group ; wpi.edu
UTD Dr. Hoi Lee ; utdallas.edu
MOSFET papers free download
BSIM3v3
Manual, (Final Version), Yuhua Cheng, Mansun Chan, Kelvin Hui, Min-chie Jeng,
Zhihong Liu, Jianhui Huang, Kai Chen, James Chen, Robert Tu, Ping K. Ko,
Chenming Hu Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley, CA 94720, from
http://www-device.eecs.berkeley.edu/~bsim3/ftpv330/Mod_doc/b3v33manu.tar
Compact
Modeling of Drain and Gate Current Noise for RF CMOS, , R. van Langevelde
Noise Modeling for RF CMOS Circuit Simulation , A.J. Scholten et
al., IEEE Trans. Electron Devices
RF-Distortion in deep sub-micron CMOS technologies , R. van
Langevelde et al., IEDM 2000 Technical Digest, pp. 807-810, 2000 (259kB).
Accurate thermal noise model for deep sub-micron CMOS , A.J.
Scholten et al., IEDM 1999 Technical Digest, pp. 155-158, 1999 (264kB).
Effect of gate-field dependent mobility degradation on distortion
analysis in MOSFET’s , R. van Langevelde and F.M. Klaassen, IEEE Trans.
Electron Devices, Vol. ED-44, pp. 2044-2052, 1997 (264kB).
90 nm Node CMOS Technology Comparison between INTEL Corporation and
SAMSUNG Electronics , Min Chin Chai, 2003, http://shay.ecn.purdue.edu/~ee612/2003fp/Chai612.pdf.
Advanced Model and Analysis of Series Resistance for CMOS Scaling Into
Nanometer Regime—Part II: Quantitative Analysis, Seong-Dong Kim,
Cheol-Min Park and Jason C. S. Woo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.
49, NO. 3, MARCH 2002
