vhdl tutorial and example

Collection of examples

HDL (Hardware Description Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs.

examples have been simulated by Aldec ActiveHDL Simulator and Synopsys Design Analyzer, as well as synthesized with Synopsys Design Compiler . Several sequential design examples have been successfully tested on Xilinx Foundation Software and FPGA/CPLD board.

This is for the vhdl beginners,

donot go through details, if you are expert in vhdl

Driver Behavior Code Behavior Simulation Inverter Behavior Code Behavior Simulation
OR gate Behavior Code Behavior Simulation NOR gate Behavior Code Behavior Simulation
AND gate Behavior Code Behavior Simulation NAND gate Behavior Code Behavior Simulation
XOR gate Behavior Code Behavior Simulation XNOR gate Behavior Code Behavior Simulation
Combinational Logic Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Tri-State Driver Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Signal/Variable Example Behavior Code Behavior Simulation
Multiplexor Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Decoder Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Adder Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Comparator Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
ALU Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Multiplier Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Simple Latch Behavior Code Test Bench Behvaior Simulation Gate-level Implementation Gate-level Simulation
D Flip-Flop Behavior Code Test Bench Behavior Simulation Gate-level Implementation Gate-level Simulation
JK Flip-Flop Behavior Code Test Bench Behavior Simulation Gate-level Implementation Gate-level Simulation
Register Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
Shift Register Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
Counter Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
FSM Model Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation

Memories

Memories RAM Module Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
ROM Module Behavior Code Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
GCD Caculator Behavior Code RTL Code (FSM+D) Comparison
FSMD Modeling RTL Code Test Bench RTL Code Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
FSM + Datapath Modeling RTL Code Test Bench RTL Code Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
FSMD Modeling RTL Code Test Bench RTL Code Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
FSM + Datapath Modeling RTL Code Test Bench RTL Code Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
FSM + Datapath Modeling RTL Code Test Bench RTL Code Simulation Gate-level Implementation Synthesis Schematic Gate-level Simulation
FIR Digital Filter (DSP Example) Data-Flow Modeling Behavior Code Test Bench Behavior Simulation(1,2) Gate-level Implementation Synthesis Schematic Gate-level Simulation
Counter Behavior Code Sythesis Script File Timing Report
FIR filter Sample Synthesis Script Comparison Table Banana Curve