rfic design flow

1. System Level Specification: The system-level specification is the first item in a typical RF-ASIC design flow (Figure-1) . One can use specification for wireless local area networkor bluetooth or some other parameters as an input for the start of the design. Given a broad specification like this one, there is a host of different ways to implement the system.

2. System Analysis and Architecture Choice: This is most critical step in RF ASIC design flow. It needs lot of analysis and research on different architectures. But now, since chips are so highly integrated and are, in reality, systems-on-a-chip, the IC designer must be involved at this level to ensure that optimal choices and proper trade-off are made in order for chips to be produced correctly. At this point in the design flow, We may use a combination of CAD tools (some system level simulators) and hand calculations to come up with the system analysis and architecture choice.

3. Chipset partitioning and chip level specifications: The architecture is then partitioned into separate chips. For instance, We may divide the architecture into transmitter chip and a receiver chip, or between a full transmit/receive chip that operates at the RF, and another chip that works at the intermediate frequency (IF). Another option is to split the functions among several chips. We will combine all the blocks to complete the design. Partitioning also involves technology selection — whether or not to utilize standard CMOS, bipolar CMOS (BiCMOS), or gallium arsenide. In most cases, CMOS is used for lower frequency, while higher frequency circuitry is based on bipolar processing. These trade-off are determined before actually starting the IC design. For this RF transceiver ASIC, BiCMOS or SiGe process may be better over CMOS technology.

4. Preliminary RFIC design topology trade off: By now, the system spec has been developed into a chip-level spec, and each block inside the chip is reviewed and analyzed for topology trade-off or for actual selection of the optimal topology. For example, there may be two ways to design a low-noise amplifier (LNA), and you’ll want to closely investigate both to achieve the best performance in this particular realm of the design.

5. Detailed Design Phase: The detailed design phase is the point where 90% of the work is done to make the IC a reality. Include all the parasitic of the design, package models, and all models of the IC. The design is simulated over the specified temperature range and worst-case process variations to make sure the design is centered and robust. Then, it’s time to move to layout. Due to the RF IC’s high frequency and high level of integration, there are crucial interactions between blocks, determined by how they are laid out and in what relative orientation. For this reason, this portion of the design is an art form. Currently, the majority of RF ICs continues to be laid out by hand; they are not auto-routed like large digital ASICs are. So a considerable amount of care must be taken, for example, in substrate connections and grounding. In higher frequency the metal layers connecting different blocks will be treated as transmission lines. Impedance mismatch should be taken great care for the layout. The detailed design schematic is converted into a physical implementation using technology files for the process.

6. RFIC Layout: Inevitably, there will be layout parasitics that can have an adverse effect on RF performance. Therefore, parasitic extraction is performed by calculating capacitance between nodes, parasitic capacitance, and resistance to the substrate. These are parasitics that couldn’t be predicted before layout.

7. Parasitic Extraction and simulation: The parasitic values are extracted using the design tool and are then inserted back into the detailed design schematics for a simulation to make sure the design is still centered and works over process and temperature variations. This represents the final simulation. The design as it is physically implemented is what is simulated, and this is the expected result after the device is tested.

8. Fabrication: After verifying the rule files provided by the vendor, The final layout to be given to the fab lab for fabrication.

9. Evaluation to Specification: This is one great exercise for a designer. We will compare between the simulated value and actual measured value. We can analyze the chip and will improve the design parameters in the subsequent stages.


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RFIC LINKS
RFIC research groups:

Alabama Microelectronics Science and Technology Center (AMSTC) at Auburn University

Auburn University Wireless Research & Education Center

Berkeley Wireless Research Center

Caltech High-Speed Integrated Communications Group

Carleton University Electrical Engineering (Plett, Rogers, and others)

Columbia University Integrated Systems Lab (CISL)

Georgia Tech Microelectronics Research Center (MiRC)
Group

Georgia Tech Microwave Application
Group

Hong Kong University of Science and Technology (HKUST) Analog Group

William Kuhn’s page at Kansas State University

K.U.Leuven MICAS Group

McGill RFIC Group

MIT High Speed Circuits and Systems Group

Ohio State Analog VLSI Group

Stanford SMIrC Laboratory

Texas A&M Analog and Mixed Signal Center

University of Alberta Electrical Engineering

UCLA Electrical Engineering

UCLA Asad Abidi Group

UCSD Center for Wireless Communications

University of Michigan Integrated Devices and Circuits Group

University of South Florida Center for Wireless and Microwave Information Systems Group

University of Texas at Arlington RFIC Group

University of Toronto Electrical Engineering

Virginia Tech Center for Wireless Telecommunications

Fabrication:

Canadian Microelectronics Corporation (CMC)

MOSIS Fabrication

TSMC Foundry

Tools:

Cadence Spectre RF
Notes

EEsof Knowledge Center

ASITIC home page

LATEX Style Files

LATEX Intro, and Primer

Conferences

CCIC 2004
European Microwave Week 2004
ESSCIRC 2005
ISCAS 2005
ISSCC 2005

We are entering a time when wireless communication becomes a necessity of everyday life. Unlike 30 years

Challenges in RFIC design
Few years ago when RF systems can only been seen in the so-called high-technology systems such as radar and satellites, they are more commonly seen in mobile phones, blue tooth interfaces, and wireless networks. As a result of mass production, they are no longer expensive and come to every household. In China, 1 million mobile phones are produced each day. Although systems based on GXXXXX still dominate the mobile communication market in China, it is the government’s resolution to carry out the 3G system before 2008 Olympics. And what comes next? The digital TV, will be populated with in 5 years. Beside the Cable based transmission system, territorial transmission is more cost effective and suitable for portable devices. China has founded its own protocol for Digital Video; in the near future can we experience a revolution in TV broadcasting which will ends the traditional analog broadcasted signals. We can see that every newly developed protocol in wireless communication will bring a huge market for the hardware supplier, and mainly the RF block, which is still a bottle neck for these devices. Such examples can also been demonstrated in the locatio n technologies such as GPS and we may also see a boost demand for RFICs for the newly developed Galileo systems.

Next, let us see some technological aspect of realizing these various kinds of RF systems. Here we consider the normally used frequency range for commercial communication: 60MHz -2.4GHz. When it comes to RF circuits or systems design, we always consider the following parameters which are often conflicting with each other: Noise Figure and Power gain which related to the system sensitivity, power consumption, dynamic range, phase noise for the Osclattor and Mixer gain for the mixer, plus the image-rejection rate and channel selectivity in a system aspect.

So an ideal RF front-end needs an amplifier with no noise, infinite dynamic rage as well as an adjustable gain with an infinite potential, an Osc with no phase noise, a mixer with infinite dynamic rage, and a filter with a perfect rectangle window in frequency domain. However, this never happens.

In industry, it is commonly admitted that bipolar technology is suitable for this frequency band. Transistor based on SiGe show more figure of merits in its performance but is more expensive. And it is a waste of money to use more advanced technologies such as HEMT and MESFET in the commercial receiver design of this frequency band. So there comes a saying that: If it can be done in CMOS, it will be done in CMOS.

The state of art technology of CMOS process enables the transistor has a Ft as high as dozens of giga hertz (now could be hundred giga hertz in 45nm CMOS), which is adequate for the circuit design in 60MHz -2.4GHz. Using CMOS to design a RF circuit seems to be a fairy tale 30 years ago, and now it became the trend for the commercial RFIC design. It has to be noted that CMOS is famed for its low power consumption in digital circuits, but here it is not equally claimed for RFIC – CMOS has a higher noise and consumes more power compared with bipolar in RF amplifier, but nevertheless, it is cheap!

Anyhow, engineers are always trying to design circuits in CMOS that has a comparable performance with bipolar circuits yet have lower costs. That is what the CMOS RFIC designers are paid to do. A successfully designed chip in CMOS can definitely gain a huge success in the market, and beat its rivals in other technologies.

According to the wide applications of RF systems, it seems that we can expect a bright future in the realm of RFIC design, but before we can imagine how promising it is, let us consider some challenges that we are facing with by a technological and industrial view.

It is a trend to integrate all components in one packet, to reduce to cost and device size, and ease the design for system designer. There are two ways to achieve this: SOP and SOC. SOP – system on package means all components are integrated in a package; advances in manufacturing and packaging technology will allow combining multiple semiconductor chips with high-Q passive elements in a single lightweight package at a low cost. SOP can be relatively easily designed and reduce the Time-to-market. However, once CMOS SOC can achieve the same functionality and performance with the SOP, SOC will sell more since it will be cheaper. It comes to it again: it will be done in CMOS, at least in frequency range below 5 GHz.

To design RF circuits in CMOS is not an easy task, as you may see that only a few companies succeeded in designing an SOC fully CMOS. CMOS used to be optimized for digital circuits only and only since recent years had it received renewed attention for analog applications. The main challenge in design CMOS RFIC is: noise, speed, mismatch, large spread, poor quality of passive elements, large power consumption and limited dynamic range. Unfortunately, these elements again seem to be conflicting. The noise performance is not as good as bipolar, so matching is very important, but CMOS has large spread; to increase the gain you have to increase the device current; and the faster the transistor can be, which means the smaller the future size is, the smaller dynamic range it will be; you can not get a good channel selection for the on-chip inductors has poor Q.

So most of the time, designers have to use special design tricks for CMOS RF circuits. Such as automatic tuning, Q enhancing, and automatic gain control. Not only in analog domain, but also in digital domain by introducing the logic circuit for circuit control. Fortunately CMOS can sustain complexity (if no more inductors are used) since most elements all have small size, as long as the circuit performance can be achieved.

Up to now, there are few domestic companies have succeeded in design and marketing CMOS RFICs. While some companies has some success in designing RFIC in bipolar or BiMOS. Indeed designing CMOS chips is difficult, one reason behind this is that, though CMOS is cheap, but RF CMOS is not cheap, in the developing phase. Before mass production, designers must be sure that everything is all right, since it will cost 100 000$ to fabricate a wafer in 0.18 CMOS – failing can directly lead to the collapse of the design house. RFIC market is a cake that every IC Company in the world wants to get a piece. By no means there are fierce competitions in this realm. How can a small company survive when it is facing with semiconductor Giants like TI, AD, INTEL, MAXIM… most of which have their own process technology? But miracle always happens, in United States, many small companies focusing on RFIC design became winners against large companies. So it has to admit that design technology is still a key- role in RFIC design.

3 thoughts on “rfic design flow

  1. RFIC designers face several significant challenges. Large RFICs, such as wireless transceivers, contain analog and digital components including voltage-controlled oscillators (VCOs), phase locked loops (PLLs), mixers, filters, amplifiers, automatic gain control (AGC) loops, digital-to-analog converters (DACs), and analog-todigital converters (ADCs). Characterizing these elements requires detailed simulation in the time- and frequencydomains. In addition, simulating multiple radio elements cascaded to form a complete transceiver chain often exceeds the limits of traditional EDA tools. Too often designers are forced to compromise on the breadth of their verification simulations due to long simulation run time and short design schedules. New technology is needed to provide the accuracy and robust convergence required for sensitive analog blocks and the capacity and speed necessary for handling the large numbers of transistors and parasitic elements typical in mixed-signal SoC designs.

    Modern radio systems operate at GHz frequencies under advanced signaling methods like orthogonal frequency division multiplexing (OFDM) and fast frequency hopping to maximize link reliability and minimize interference with other services. Circuits that perform at high frequency with high switching speed are extremely sensitive to active and passive device models, distributed layout parasitics, substrate coupling effects, inter-stage impedances, IC packaging, and power supply noise. Providing new methods that accurately characterize layout and other parasitic effects is more critical than ever to first pass success.

    RFIC design requires specialized and unique analysis techniques specific to RF design. Nonlinear effects of harmonic distortion, gain compression, oscillator phase noise, and mixer noise figure are most often simulated and reported in the frequency domain. Switching behavior, circuit initial start-up, and transceiver response to instantaneous events such as frequency hopping are best examined in the time domain. Technology to allow simulation in the time- and frequency-domains with consistent results between is required for modern RF circuit simulation and verification.

    Integrated circuits are eventually assembled into an IC package. In many cases, RF circuits are added to large SoCs in a single-chip solution. Another approach is to integrate RF circuitry by using system-in-package (SiP) techniques leading to similar verification challenges as found in SoC solutions. The most comprehensive system approach allows for a multi-die package that may include a digital SoC together with wireless, sensor and actuator die as necessary.

    New technologies for circuit simulation capacity and speed that add value to a ready established flow can be integrated into existing design solutions. For analog and RF circuits, the most popular flow is the Cadence Virtuoso® Analog Design Environment (ADE). Ansoft’s products for advanced circuit and electromagnetic simulation are linked into that environment. Many RFICs contain the analog-to-digital converter (ADC), digital-to-analog converter (DAC), phase-lock loop (PLL), and possibly a digital synthesizer. These functions are generally created through a different environment and integrated on-chip. Verification of these blocks is still performed using SPICE-level circuit simulators for critical accuracy. The addition of Nexxim® new technology for high-performance circuit simulation combined with the reliability of the High-Frequency Structure Simulator (HFSS™) component and layout electromagnetic extraction into the design flow creates new opportunities for SoC designers to achieve firstpass silicon success.

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