vlsi interview question and answer


Custom Search OUR FAVORITES EDA BOARD Forum by the engineers for the engineers http://discussion.rficdesign.com RF DESIGN RF Design links and resources, free download software, books, research papers,projects... http://rf.rficdesign.com INTERVIEW QA Interview questions and answers, VLSI, RF, Analog, electronics and common http://links.rficdesign.com SITE MAP All about resources and links , research papers, free download papers, projects, software and much more	Interview question and answer : VLSI, ASIC, analog integrated circuit, RF and RFIC VLSI design interview question with answers1 VLSI design interview question with answers2 VLSI design interview question with answers3 Analog IC Techniques , most common questions in telephonic interview Question paper for analog design interview Another Question paper in analog integrated circuit design One old Question paper for Texas instruments, India, (collected) Analog rfic interview preparation VLSI design interview questions1 VLSI design interview questions2 VLSI design interview questions3 Logic , memory design VLSI interview questions RF design interview question general HR interview type General interview questions with answers Preapring for your interview Commonly asked interview questions Common entry level questions Common interview questions good to look at it not categorised General Electronics and communication interview question Typical RFIC design flow, The design flow will vary from company to company Typical WLAN block diagram basic analog design reports adaxas Web Directory Question1: What is Slew Rate and how is it used to design an op amp? Answer: Slew Rate (SR) is the rate at which the output voltage changes for a large scale change in voltage at the input. Thus SR is in units of volts/time. The design project specifies SR is 400nsec for a 1 volt step. This means that SR = 1V/400nsec = 2.5V/usec. Note: the slew rate is not a time, but a rate (1/time). You will use the specification given for slew rate to determine the bias current of the differential stage, since this is the limiting charging time* (see note below). Thus you can calculate, Ibias > (SR)(Cc) and set Ibias so that it is greater than the product of the slew rate times the compensation capacitance. This equation is derived from the basic relations of Q = C V = I t, where Q is charge and t is time. When you calculate this value it will be rather small, and I suggest you use a current value slightly larger, maybe even 5-10 times larger, to insure you meet the SR specification. * (note from above) The slew rate is limited either by the output of the differential amplifier or the output of the second stage, whichever is the slowest at charging the output capacitance. You can determine this from t = (C)(V)/(I) If we assume that we are interested in changing the charge to give a 1 volt change in output (as in your design project), then we can calculate each of these to charging times from t = Cc/Ibias, for the differential stage t = Cl/I6, where Cl is the load capacitor, I6 is the current in the second stage, for the second stage (Note that both of these equations assume that the node capacitance will be dominated by Cc and Cl, which is generally a good assumption). Since Ibias is normally much smaller than I6, the slew rate is typically limited by the differential stage and thus we write, SR = Ibias/Cc. However, you should probably check to see which of these time constants is the largest, and if you find that the second stage stage is longer, then you should adjust the currents so that SR = I6/Cl. How is the cost of fabrication related to IC die size? How the die size affects yield factor? Let us take an example: Size of a wafer=6 inch Size of a single die=1mm X 1mm Cost of a 6 inch wafer=$2000 Then the total no of die could be approx No. of die=total area of wafer/area of a single die =(3 X 3 X 2.54 X 2.54)/(0.1 X 0.1) =18232 Therefore cost of single die=$2000/18232 =$0.109 A wafer of ICs will cost the same to fabricate whether it contains 10 000 circuits or 100 circuits. Clearly the larger the area the circuit occupies, the more expensive the die. This is compounded by the fact that larger die will also exhibit lower yields. Figure is a graph showing the number of die available from a single wafer versus die size. Wafer diameters of 3", 4" and 6" are considered. The figures take account of the area lost to circuits at the edge of the wafer and make an allowance for area devoted to Process Control Monitor (PCM) cells. Functional yield is not considered since this is a complex function of process defect density, device variation, circuit design and performance specification. However it is certain that yield will degrade with increasing die size