Frequenccy Synthesizer

• Introduction
  
  Phase-Locked Loop (PLL) circuits are used for frequency control. The circuit operation is basically a feedback system that controls the phase of a voltage-controlled oscillator (VCO).
  The input signal is applied to one phase detector input. The other input is connected to a divide-by-N counter output. Normally the frequencies of both signals will be nearly the same. The phase detector output is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter. The loop filter determines the PLL's dynamic characteristics. The filtered signal controls the VCO. Note that the VCO output is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase detector via the divide-by-N counter.
  Normally, the loop filter is designed to match the characteristics required by the PLL's application. If the PLL is to acquire and track a signal, the loop filter bandwidth will be greater than if it expects a fixed-input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies the PLL will follow is called the tracking range. Generally, the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth, the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
  
  
  PLL Modeling with Verilog-A
  Transistor level simulation of PLL is very time consuming. At the initial design stage, we need to know some parameters, for example the bandwidth of the PLL, to see if the PLL meet the requirements (for example lock time) or not. At this stage, a modeling enable fast simulation is very useful. Another important advantage of PLL modeling is the chip (or system) level simulation. For example PLL is just a function block of a chip. At this level simulation, we do not want the transistor level simulation of the PLL, or even worse, with the transistor level PLL, the chip simulation may never be done because the extreme long time simulation. The models also enable the top-down design methodology. The following are some Verilog-A modeling of the PLL. You can download them and use them. All models have been tested using Cadence Analog Artist Spectre simulation tools. Any questions, feedbacks, please email me. Thanks. PFD followed by Charge Pump with jitter VCO with jitter Frequency divider Frequency divider with jitter Instantaneous Frequency Meter This model let you detect the instaneous frequency of the clock signal. I used this model to detect the VCO instantaneous frequency, in this way I can check the frequency change with control voltage or other PLL parameters. RMS Cycle-to-cycle Jitter Meter This model let you to measurede the cycle-to-cycle jitter (rms) of the inout clock signal. The input signal is the clock signal under test, the output signals are the cycle-to-cycle jitter and the total number of the periods that have been measured. Theoretically speaking, this number should be infinity. If you want to use this model, you need to modify the code according your power supply. In this version shown here the power supply is 2.5V and the the parameter hlfvcc is 1.25; If your power supply is not 2.5V, you need to change this hlfvcc accordingly.
• PLL Fundamentals application note from motorolla
  
  
• fractional-N synthesis ; article from TI
  
  
• PLL modeling and simulation ; designers-guide.com
  
  
• Wideband modulation of PLL's
  
  
• Fractional-N synthesizers
  
  
• PLL design Class notes ; ece.gatech.edu
  
  
• Loop filter design Class notes ; stanford.edu
  
  
• Thesis on fractional-N synthesizers
  
  
• PLL dynamics
  
  
• Delta-Sigma PLL's
  
  
  
  
  
  
  
  
  
  
  
• phase noise theory
  
  
• Frequency Control Symposium
  
  
• Principles of PLLs
  
  
• Low-Noise Oscillator Design
  
  
• PLL article good article
  
  
• PLL design ; white papers
  
  Software for PLL Design
  
  
  
• PLL phase noise calculator
  
  
• Free PLL analysis
  
  
• phase noise ; mathcad routine
  
  
• Automated PLL Synthesis
  
  
• National's PLL Design Software
  
  
• Digital Phase Locked Loop Design
  
  
• EASY PLL Simulator
  
  
• Mathcad routines for PLL Analysis
  
  
• Applied Radio Labs
  
  
• SimPLL ; PLL simulator
  
  
• PLL calculator
  
  
• 3rd order PLL design ; online application
  
  
• Simulink ; communication system toolbox
  
  
• Direct digital synthesis
  
  
• Virtual Silicon
  
  
• Mathsoft.
  
  
• Articles on PLL design
  
  Spurs and Phase Noise
  
  
  
• Techniques for Measuring Phase Noise
  
  
• Crystal oscillator library
  
  
• Substrate Noise in Mixed-Signal ICs ; substrate noise coupling
  
  
• IEEE Electromagnetic Compatibility Society
  
  
• Crosstalk Articles
  
  
• Inductance nags ; Papers on inductive spur coupling
  
  
• phase noise
  
  
• ground loop problems
  
  
• aritcle on ground noise
  
  
• ground loops
  
  
• noise coupling in cellular handsets.
  
  
• Circuit layout techniques
  
  
• EMC aricles ; reactive coupling
  
  
• on-chip RF isolation techniques
  
  
• SPACE : Substrate Coupling Software