Analog and RFIC Layout

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• Lecture notes MOS Capacitances, Passive Components, and Layout
  
  
• Matching of Resistors and Capacitors
  
  
• Good introduction on tanner tool includes device modelling
  
  
• lecture notes2 ,classes.yale.edu
  
  
• lecture notes3, uta.edu Semiconductor Device Modeling and Characterization
  
  
• Cadence tutorials with inverter example
  
  
  
  
  
  
  
  
  
  
  
  
• lecture notes4 from iastate.edu
  
  
• OP AMP layout
  
  
• introduction for layout in cadence tool, includes device matching
  
  
• Lecture notes on analog layout and device physics
  
  
• From engineering.ucsb.edu
  
  
• lecture notes from stanford.edu
  
  
• Analog integrated circuit design methodology
  
  
• Lectures in Analog layout
  
  
• Automatic Layout of Analog and Digital systems
  
  
• Layout Issues in Analog Mixed Signal ICs
  
  
• Layout considerations
  
  
• Layout with cadence
  
  
• Links to Information on Advanced Layout Topics
  
  
• The analog layout array
  
  overview of analog layout
  
  In doing layouts for digital circuits, the speed and the area are the two most important issues. In contrast, in doing layout for analog circuits, everything should be considered simultaneously. In addition to the speed and the area, other equally critical considerations should be taken into account.
  For example, for amplifier design, good matching in devices is necessary to minimize the offset voltage, and good shielding is required to protect critical nodes from being disturbed. Without proper layout, the mismatches and the coupled noise would be quite large and would significantly degrade the performance of the amplifiers.
  
  Free download of cmos model files from mosis.org
  
• CMOS model Files (new technologies)
  
• CMOS model Files (old technologies)
  
  
  
  
  Analog IC and layout Design Software
  
  
• Analog Office from Applied Wave Research
  
  
• Cadence www.cadence.com
  
  
• Mentor Graphics www.mentor.com
  
  
• Tanner Tools www.tanner.com
  
  
• RF Design Environment from agilent
  
  
• Stabie-Soft
  
  
• Magic The original layout editor. Free
  
  
• LASI free layout editor for windows
  
  
• WinVLSI free layout editor tool for windows
  
  Some analog layout Issues
  
  Matching of Devices:
  Matching of individual devices is of paramount concern in analog circuit design. Infact almost all of the 'analog layout techniques' are actually methods for improving matching between different devices on a chip. Matching is important because most analog circuit designs use a ratio based design technique(e.g. current mirrors). Some common techniques that help improve device mathcing are MULTI-GATE FINGER LAYOUT and COMMON-CENTROID LAYOUT.
  
  Noise:
  Noise is important in all analog circuits because it limits dynamic range. In general there are two types of noise, random noise and environmental noise. Random noise refers to noise generated by resistors and active devices in an integrated circuit; environmental noise refers to unwanted signals that are generated by humans. Two common examples of environmental noise are switching of digital circuits and 60 Hz 'hum'. In general, random noise is dealt with at the circuit design level. However the are some layout techniques which can help to reduce random noise. MULTI-GATE FINGER LAYOUT reduces the gate resistance of the poly-silicon and the neutral body region, which are both random noise sources. Generous use of SUBSTRATE PLUGS will help to reduce the resistance of the neutral body region, and thus will minimize the noise contributed by this resistance.
  
  Enivironmental noise is also dealt with at the circuit level. One common design technique used to minimize the effects of environmental noise is to employ a 'fully-differential' circuit design, since environmental noise generally appears as a common-mode signal. However SUBSTRATE PLUGGING is also very useful for reducing 'substrate noise', which is a particularly troublesome form of environmental noise encountered in highly integrated mixed-signal systems and Systems-On-a-Chip (SOC). Substrate noise occurs when a large amount digital circuits are present on a chip. The switching of a large number of circuits discharges large dynamic currents to the substrate, which cause the substrate voltage to 'bounce'. The modulation of the substrate voltage can then couple into analog circuits via the body effect or parasitic capacitances. SUBSTRATE PLUGGING minimizes substrate noise because it provides a low impedance path to ground for the noise current.
  
  Note:
  Issues that are important in digital circuits are still important in analog layout. Foremost among these is parasitic aware layout. It is important to minimize series resistance in digital circuits because it slows switching speed. Series resistance also slows analog circuits, plus it introduces unwanted noise. Parasitic capacitance is avoided in digital circuits because it slows switching speed and/or increases dynamic power dissipation. Stray capacitance has the same effect in analog circuits (bias current must be increased to maintain bandwidth and/or slew rate when extra load capacitance is present) plus it can lead to instability in high gain feedback systems.
  
  
  
  MULTI-GATE FINGER LAYOUT refers to implementing a single, wide transistor as several narrow transistors in parallel. This minimizes the gate resistance and it also makes it easier to match the transistor with other devices. When referring to a multiple gate finger device one usually uses the term 'M-factor' to refer to the number of gate fingers. Therefore an M=4 device has 4 gate fingers.
  
  Note: When trying to ratio two or more devices you should always use the same unit transistor size for each device and then include multiple gate fingers to achieve the desired ratio. For instance, a current mirror containing a 10/2 and 5/2 device is NOT a perfect ratio of two because of oxide encroachment. However a 5/2 M=2 device and a 5/2 M=1 device is a perfect ratio of two.
  
  COMMON-CENTROID LAYOUT refers to a layout style in which a set of devices has a common center point. This is used to minimize the effect of linear process gradients (e.g. oxide thickness) in a circuit.
  Example: Consider that a transistor 'A' has 'M' fingers and can be represented by 'M' instances of the letter 'A'. For example 'AAAA' represents a transistor 'A' that has 4 fingers.
  Now consider the layout of two transistors, 'A' and 'B'.
  One structure is: AABB
  The problem with this structure is that the transistor 'A' will have a different oxide capacitance (which affects transconductance, Ft) than 'B' because of oxide gradients. For instance, if the oxide thickness at the center of the structure is Tox, and there is an oxide gradient DEL, the average oxide thickness for 'A' and 'B' is
  Tox(A, average) = [Tox - 2DEL]/2 + [Tox - DEL]/2 = Tox - 3DEL/2
  Tox(B, average) = [Tox + 2DEL]/2 + [Tox + DEL]/2 = Tox + 3DEL/2
  Now consider the following layout: ABBA
  The average oxide thickness will now be:
  Tox(A, average) = [Tox - 2DEL]/2 + [Tox + 2DEL]/2 = Tox
  Tox(B, average) = [Tox - DEL]/2 + [Tox + DEL]/2 = Tox.
  Many other common centroid layout structures are possible:
  ABCCBA, ABBBBA, ...
  Also in two dimensions:
  AB BA OR ABAB BABA ABAB BABA
  
  
  SUBSTRATE PLUGGING simply refers to making an ohmic contact to the substrate. This technique is used in digital circuits to minimize latch-up. In analog circuits it is used to minimize latch-up and for the reasons discussed above.
  
  
  Design Tools for Layout
  Layout design rules, process parameters and SPICE models are available for MOSIS processes . Projects submitted to MOSIS for fabrication can be designed using either layout design rules specific to a process (vendor native rules) or vendor-independent, scalable rules (SCMOS rules). Users can access technology files for a variety of CAD tools (e.g. Cadence, Mentor) for vendor rules via the MOSIS secure document server or the SCMOS layout rules for the following tools.
  
  Cadence
  MOSIS supports technology files for SCMOS and vendor rules.
  Some members of the Cadence University Software Program have created design kits, technology files, etc., for various MOSIS processes using SCMOS rules. One key example is the NCSU Cadence Design Kit (CDK), which focuses on supporting full-custom CMOS IC design.
  Virginia Tech offers a standard cell library for the TSMC 0.25 process technology based on MOSIS SCMOS_DEEP rules for use with Synopsys synthesis and Cadence place-and-route tools.
  USC Asynchronous CAD/VLSI Group developed asynchronous standard cell libraries/templates that support Cadence DFII files for the TSMC 0.25 process technology, and are available on the MOSIS secure document server. Look for USC PCBH 025 or USC STFB 025 in the TSMC25 logic section. Access is restructed, account number and document password are required.
  www.cadence.com
  
  Mentor Graphics
  Mentor Graphics supports Technology Design Kits for Mentor's Analog/Mixed-Signal IC Flow, including kits for several processes accessed by MOSIS. for more information, please refer to
  
  - Mentor Nanometer IC Design Environment
  - Mentor Technology Design Kit
  - Higher Education Program for the ASIC Design Kit
  www.mentorg.com
  Silvaco
  Silvaco provides analog and mixed-signal IC design tools including simulation, physical design and verification with links to Mentor Calibre tools. Foundry design kits are available for AMIS 0.50 and TSMC 0.18 processes. A MOSIS SCMOS design kit is also available from Silvaco.
  www.silvaco.com/products/AMS.html
  
  Tanner
  Tanner Research offers IC design tools, (layout, verification and simulation) that run on Windows based PC's. The tools specialize in analog and mixed-signal IC and MEMS design. All processes accessed by MOSIS are compatible with their family of tools. Tanner design kits, L-Edit process technology setups, design services, and classes are available from Tanner Research.
  www.tanner.com
  
  IC Editors
  IC Editors provides IC Layout & Verification Software for PCs. DRC and LVS files have been contributed.
  www.iceditors.com
  
  Laytools
  LAYTOOLS is a custom IC design suite that includes layout, verification, place/route, schematic capture, and industry standard database conversion and support tools. It is intended for mixed-signal, analog, and digital IC design and operates on Windows, Linux, and UNIX. SCMOS (Scalable CMOS) verification decks for LAYTOOLS are available, as well as standard cell libraries and I/O libraries. LAYTOOLS is available through Vertechs Integrations, Inc. an affiliate of the MATRICS Group.
  www.laytools.com
  
  Electric
  The Electric Design System is a complete Electronic Design Automation (EDA) system. The Electric source code has been given to the Free Software Foundation. Technologies files for MOSIS technologies are part of the default installation.
  www.staticfreesoft.com
  
  LASI
  LASI is a PC-based layout system. The associated textbook is CMOS Circuit Design, Layout and Simulation. LASI is available in DOS and Windows versions.
  
  Magic
  Magic is a popular integrated circuit layout tool in common use in universities and a number of industrial sites. Magic comes with source code and a relaxed copyright that allows you to redistribute it, modify it, and generally do what you want with it.
  http://vlsi.cornell.edu/magic
  
  Zeni EDA
  Zeni provides schematic editor, schematic simulation, schematic driven layout, layout editor, layout verification, parasitic parameter extraction, and signal integrity analysis. Zeni Systems is available through HED (CEC Huada Electronic Design).
  www.hed.com.cn/english/ProductsCenter/ZeniEDASystem.asp
  analog layout analog layout techniques tutorials on layout of analog integrated circuit analog layout design