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Analog Integrated circuit
Tutorial, Research papers, Lecture notes, Free download, faq, thesis, Resources, .....
Introduction
The continuing development of silicon technology and the growing demand for more signal processing and functionality integrated on a single chip, has resulted in a growing need for the design of effective analog integrated circuits.
Analog circuits and systems have an important role in the implementation and application of silicon technology across a wide range of frequencies and for many functions. At all stages in the economic cycle having circuit designers with effective analog skills can give organisations a vital competitive edge, so they need to ensure that their engineers are appropriately skilled in their understanding of analog design techniques to meet current needs.
The reduction of power consumption in analog integrated circuits inevitably leads to higher noise levels, presenting a major challenge in present-day circuit designs. This course aims at developing design guidelines towards achieving optimum performance for low power and low noise simultaneuously.
Moreover the bipolar transistors, which are available in BiCMOS technologies, always offer less power consumption for the same equivalent input noise, which results in a renewed interest in BiCMOS. In this site BiCMOS and CMOS are treated in parallel, with many actual circuits designed and compared.
A 147 dB Dynamic Range Electronic
Attenuator for Audiometric Applications with On-Chip 1 W Power
Amplifier
Francesconi F., Micronova Sistemi
S.r.l.
A 2.8V 200MHz Replicating Current
Comparator for Convolutional Decoders
Demosthenous A.,
University College London
A Dynamically Controllable DC/DC Level
Converter and Its Application to High-Speed, Low-Power
Circuits
Enomoto T., Chuo
University
A low-power microphone preamplifier with
EMI canceling
Reitsma G., Delft University of
Technology
A packaged low-noise high-speed regulated
cascode transimpedance amplifier using 0.6µm N-well CMOS
technology
Park S.M., Imperial
College
A Receiver Channel with a Leading Edge
Timing Discriminator for a Pulsed Time-of-Flight Laser
Radar
Peltola Te., University of
Oulu
APD Implementation to GHz Range Receiver
Channel for a Pulsed Time-of-Flight Laser Radar
Pennala R.,
University of Oulu
Battery Supplied Low Power Analog-Digital
Front-End for Audio Applications
Klootsema R., Xemics
SA
Curvature Compensated BiCMOS Bandgap with 1
V Supply Voltage
Malcovati P., University of
Pavia
New Regulated Voltage Down Converter based
on Modified Band-Gap Cells
Barthélémy H.,
ISEM
Ultra-low Voltage CMOS Cascode
Amplifier
Lehmann T., Technical University of
Denmark
- A. Abo, K. Onodera,
"Impact of Device Scaling on Analog Power Consumption",
- A. Abo, N. Cobb, J. Yan,
"A modem for digital data storage on audio tape"
- ANALOG UNIVERSITY from national semiconductor
- Research groups in analog and mixed signal design
- Analog Integrated Circuit Course
- Analog VLSI Design Lab Assignments ohiou.edu
- ANALOG Design research papers
- Silicon Foundries
- EE140 Analog Integrated Circuits
- Spice simulation softwares free downloads
- Good lecture on OP AMP layout
- RESEARCH PAPERs: operational amplifier
- A. Abo, S. Mehta,
"A Compact Current-mode Full Adder"
- A. Abo, N. Cobb, J. Yan,
"Digital Storage on Audio Cassettes,"
- Analog Electronics ece.gatech.edu
- CMOS Analog Filter Design from toronto.edu
- Lecture Notes on Analog Integrated Circuit
- EE501_analog integrated circuit course
- ALL SPICE STUFF Page
- Advanced Analog Circuit Design Techniques
Course material from http://amesp02.tamu.edu
- Circuit Diagrams,Design Notes
- Design and Simulation of Operational Amplifier
Design and Simulation of Operational Amplifier USING MENTOR GRAPHICS
- EE Times Design Library
Analog Design, Communications design, Design automation, Embeded syytems design
- Index of papers from stanford university
- MOS Analog Integrated Circuit Design
A Review of MOS Device Physics ,Bandwidth Estimation Techniques ,The Miller Effect and Pole Splitting
- MS and PhD theses BERKELY
A/D Conversion,RF Transceivers and Building Blocks,Analog CAD
- OP AMP basics, design and applications
- PCB libraries for Protel DXP, PCAD, PADS, Cadstar, Eagle and many more
- Research in Analog IC design
- SIlicon IC periodic table
- Semitrends People, News and Technology in the Semiconductor Industry
- Slides by David Johns (Toronto)
- Solid-state LC Oscillators
- Audio and video lectures analog, rfic and cmos design
Download thesis and research papers from berkeley.edu
- Transreciver and filters
- PLL and DLL
- Mixer design
- Sigma delta, ADC, DAC
- One more on PLL and DLL
- Power amplifier
- CMOS LNA
- Transmitter
- George Chien,
"A Floating-Gate Programmable MOSFET using standard double poly CMOS
process," (GIF/MIF/PS)EECS231 Class Project Slides,
- George Chien,
"Programmable double-poly MOSFET," EE231 Class
Project Paper,
- G. Chien, R. Galicia, M. Wan,
"A Study of Programmable ASIC for DSP Applications,"
- G. Chien, R. Galicia, M. Wan,
"A Study of Programmable ASIC for DSP Applications,"
-
"Design Considerations for High-Speed,
Low-Power CMOS A/D Converters" (PDF)
-
"Possible Analog IC Scenarios for the 90's" (PDF)
-
High-Speed CMOS A/D Converters (PDF)
-
MOS Sample/Hold Amplifiers (PDF)
-
CMOS Voltage Comparator Design (PDF)
-
Monolithic D/A Converters (PDF)
-
Switched-Capacitor Integrator/Gain Blocks
- A. Demir, E. Liu, A. Sangiovanni-Vincentelli, and I. Vassiliou,
Behavioral Simulation Techniques for Phase/Delay-Locked
Systems (PS),
In Proc. Custom Integrated Circuit Conference, pages
- R. Neff,
"A Module Generator for High Speed CMOS Current Output
Digital/Analog Converters," (PS)
- Iasson Vassiliou, Henry Chang, Alper Demir, Edoardo Charbon,
Paolo Miliozzi and Alberto Sangiovanni-Vincentelli,
"A Video Driver System Designed Using a Top-Down,
Constraint-Driven Methodology," (PS)
In Proc. IEEE/ACM International Conference
ICCAD 96 Conference slides (PS).
- Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi
and Alberto L. Sangiovanni-Vincentelli,
"Use of Sensitivities and Generalized Substrate Models
in Mixed-Signal IC Design," (PS) In Proc. Design Automation Conference, .
Site information
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Free downlod research papers
3-D Ics: Motivation, Performance Anlaysis
and Technology
Saraswat K., Stanford
University
Analogue Design in Deep Submicron CMOS
Technology
Bult K., Broadcom Netherlands
B.V.
Bluetooth (TM): From Antenna to
Silicon
Haartsen J., Ericsson Radio
Systems
Future is in
Wireless
Neuvo Y, Nokia Mobile Phones
Future Trends in Automotive Electronics,
Sensors and Communication Systems
Neumann K.-T.,
Volkswagen AG
Software-Radio Base-Stations, A Challenge
for Analogue IC-Design
Hedberg B., Ericsson Radio
Systems
SOI CMOS Circuit Design Exposed - Another
Dirty Tricks Campaign?
Redman-White W., Philips
Semiconductors
VDSL, From Concept to
Chips
Spruyt P., Alcatel Research
Analogue
Filters
A 2.7V CMOS Dual-Mode Baseband Filter for
PDC and WCDMA
Hollman T., Helsinki University of
Technology
A 350 MHz Programmable Analog FIR Filter
Using Mixed-Signal Multiplier
Lee E.K.F., Iowa State
University
A Channel Selection Filter for a WCDMA
Direct Conversion Receiver
Jussila J., Helsinki
University of Technology
A CMOS gm-C Polyphase Filter with High
Image Band Rejection
Andreani P, Lund
University
A CMOS Switched-Capacitor Bandpass Filter
with 100 MSample/s Input Sampling and Frequency
Downconversion
Ferreira Neves R., Instituto Superior
Técnico
A Hilbert sampler/filter and complex
bandpass SC filter for I/Q demodulation
Karvonen S.,
University of Oulu
A low-distortion digitally programmable
continuous-time filter and variable-gain amplifier
Celma
S., Universidad de Zaragoza
A Micropower Class AB CMOS Log-Domain
Filter for DECT Applications
Python D., Ukom
inc
An Analog CMOS High-Speed Continuous-Time
FIR Filter
Spencer R., University of
California
An Eighth-Order CMOS Lowpass Filter with
30-120 MHz Tuning Range and Programmable Boost
Bollati G.,
STMicroelectronics
CMOS Switched-Capacitor Decimation Filter
for Mixed-Signal Video Applications
Petraglia A.,
Federal University of Rio de Janeiro
Low-Voltage Analog Filters using
Floating-gate MOSFETs
Rodriguez-Villegas E.O.,
Universidad de Sevilla
Programmable direct digital tuning circuit
for a continuous-time filter
Salo T., Helsinki
University of Technology
Data
Converters
1.0-Volt, 9-bit Pipelined CMOS
ADC
Waltari M., Helsinki University of
Technology
12 Bit Low Power Fully Differential
Switched Capacitor Non-Calibrating Successive Approximation ADC with
1MS/s
Promitzer G., Austria Mikro Systeme International
AG
A 1.8V 20mW 1mm² 14b 100MSample/s CMOS
DAC
Tiilikainen M.P., Nokia Mobile
Phones
A 1.8V MOSFET-Only Sigma-Delta Modulator
Using Compensated MOS-Capacitors in Depletion with Substrate
Biasing
Tille Th., Technical University of
Munich
A 10-bit 200 MS/s CMOS Parallel Pipeline
A/D Converter
Sumanen L., Helsinki University of
Technology
A 2.5 Volt 6 bit 600MS/s Flash ADC in
0.25µm CMOS
Scholtens P., Philips Research
Laboratories
A 2.7V 50 MHz IF-Sampling Delta-Sigma
Modulator with +37dBV IIP3 for Digital Cellular Phones
Lindfors
S., KTH
A 400MHz 5th-Order CMOS Continuous-Time
Switched-Current Sigma-Delta Modulator
Luh L.,
University of Southern California
A 73dB SFDR 10.7MHz 3.3V CMOS Bandpass
Sigma-Delta Modulator sampled at 37.05MHz
Cusinato P.,
STMicroelectronics
A Low-Power 14-b 5 MS/s CMOS Pipeline ADC
with Background Analog Self-Calibration
Goes J.,
Instituto Superior Técnico
Adaptive Noise Shaping ADC Based on LMS
Algorithm
Maloberti F., Texas A&M
University
An 8-bit 13-Msamples/s
Digital-Background-Calibrated Algorithmic ADC
Blecker E.B.,
University of California
An 8-bit, 1-Gsample/s Folding-Interpolating
Analog-to-Digital Converter
Salama C.A.T., University of
Toronto
SiGe Track-and-Hold with HD3=-87dBFS for
fck=110MHz, fin=(110MHz-1kHz) and Vin=1Vpp,diff
Gatti U.,
Siemens ICN S.p.A.
Ultra Low Power A/D Converters Using an
Enhanced Differential Charge-Transfer Amplifier
Marble
W.J., American Microsystems, Inc.
Digital
Systems and Signaling
A low power reconfigurable 12-tap FIR
interpolation filter with fixed coefficient sets
Henning
C., University of Technology RWTH Aachen
A New Contactless Smartcard IC using an
On-Chip Antenna and an Asynchronous Micro-controller
Abrial
A., France Telecom
Accurate A Priori Signal Integrity
Estimation Using A Multilevel Dynamic Interconnect Model for Deep Submicron VLSI
Design
Zheng L.-R., Royal Institute of
Technology
Dynamically Programmable Parallel Processor
(DPPP): A Novel Reconfigurable Architecture with Simple Program
Interface
Tan B.-K., Osaka
Univeristy
Front-end Processor Core for up to 64X
Speed CD-ROM Drive in 0.35um CMOS
Wada A., Sanyo
Electric Co., Ltd
Fully Integrated Motor Driver Controller
for Hard Disk Drive Using Digital Approach
Bardelli R.,
STMicroelectronics S.r.l.
Itanium(tm) Processor System Bus
Design
Venkataraman S., Intel Corp.
Optimum voltage swing on on-chip and
off-chip interconnects
Svensson C., Linköping
University
Self Calibrating and Adjustable CMOS Pad
Driver for Improved Electromagnetic Compatibility
Klein R.,
Infineon Technologies AG
Transition Pattern Coding: An approach to
reduce Energy in Interconnect
Sotiriadis P.,
Massachusetts Institute of Technology
Logic
Circuits
A Novel High Speed Low Power Logic Family:
Race Logic
Lee S.J., Korea Advanced Institute of Science
and Technology
A Skew-Tolerant Design Scheme for Over
1-GHz LSIs
Hagihara Y., NEC
Corporation
Dynamic Flip-Flop with Improved
Power
Oklobdzija V.G., University of
California
High-Speed and Low-Swing On-Chip Bus
Interface Using Threshold Voltage Swing Driver and Dual Sense Amplifier
Receiver
Yang B.-D., Korea Advanced Institute of Science
and Technology
Iterative Self-Timed Multiplier with Early
Completion
Kim D.-W., Seoul National
University
Low PowerSelf-Timed Floating-Point Divider
in 0.25um Technology
Won J.-H., Seoul National
University
Nonvolatile CMOS Latch Employing GMR
Resistors
Black W.C., Iowa State
University
Skewed CMOS: Noise-Immune High-Performance
Low-Power Static Circuit Family
Solomatnikov A., Purdue
University
Memories
A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb
Four-Way Set-Associative CMOS Cache Memory Implemented by 1.8V 0.18µm Foundry
CMOS Technology for Low-Voltage Low-Power VLSI System
Applications
Kuo J.B., National Taiwan
University
A Dual-Phase-Controlled Dynamic Latched
(DDL) Amplifier for High-Speed and Low-Power DRAMs
Fujisawa
H., Hitachi Ltd.
A High-Efficiency Back-Bias Generator with
Cross-Coupled Hybrid Pumping Circuit for sub-1.5 V DRAM
applications
Min K.-S., Hyundai Electronics Industries
Co., Ltd.
A Low Power Reconfigurable I/O DRAM Macro
with Single Bit line Writing Scheme
Kook J., Korea
Advanced Institute of Science and Technology
A Low-Power SRAM with Resonantly Powered
Data, Address, Word, and Bit Lines
Athas W., House Ear
Institute
Investigation of Cell Leakage and Data
Retention in eDRAM
Hashimoto M., Cadence Design
Systems
Source-Pulsed Dynamic-Threshold CMOS SRAMs
for Fast, Portable Applications
Bhavnagarwala A.J.,
Georgia Institute of Technology
Super-Compact Shared-Cache Memories with
Low Power Consumption for Multi-Issue Single Chip
Processors
Kishi K., Hiroshima
University
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