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	<title>RFIC Technologies</title>
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	<description>RFIC Technologies</description>
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		<title>chip level layout checklist</title>
		<link>http://www.rficdesign.com/chip-level-layout-checklist</link>
		<comments>http://www.rficdesign.com/chip-level-layout-checklist#comments</comments>
		<pubDate>Wed, 06 Feb 2013 06:49:27 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[tech]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5805</guid>
		<description><![CDATA[1. Does the chip meet all packaging requirements? ❑ Yes ❑ No ❑ N/A 2. Are the power supply connections to the pads adequate? ❑ Yes ❑ No ❑ N/A 3. Is the power supply strapping adequate and implemented with ❑ Yes ❑ No ❑ N/A enough vias? 4. Are the power lines notched anywhere [...]]]></description>
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		<title>rfic design services</title>
		<link>http://www.rficdesign.com/rfic-design-services</link>
		<comments>http://www.rficdesign.com/rfic-design-services#comments</comments>
		<pubDate>Tue, 29 Jan 2013 13:39:59 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[rfic]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5826</guid>
		<description><![CDATA[contact us for your rfic design needs, we can do from system level to chip testing.]]></description>
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		<title>What is leaf layout</title>
		<link>http://www.rficdesign.com/what-is-leaf-layout</link>
		<comments>http://www.rficdesign.com/what-is-leaf-layout#comments</comments>
		<pubDate>Tue, 29 Jan 2013 13:28:17 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5825</guid>
		<description><![CDATA[• They are repeatable layout designs that can be reused in many different regions of the chip. • They can be made out of one polygon—i.e., contact cells; can be made out of three polygons—i.e., contact cells made with the surrounding layers (metal1, metal2, via12); or can be a complete circuit—i.e., inverter, NAND, flip-flop. • [...]]]></description>
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		<title>basic knowledge for a layout designer</title>
		<link>http://www.rficdesign.com/basic-knowledge-for-a-layout-designer</link>
		<comments>http://www.rficdesign.com/basic-knowledge-for-a-layout-designer#comments</comments>
		<pubDate>Fri, 25 Jan 2013 13:53:51 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5824</guid>
		<description><![CDATA[The layout engineer should have • Detailed knowledge of the entire set of layers and layout design rules. • The size of the design, estimated from the number of transistors in the design and the layout design rules. • Attention to transistor-level placement and interconnect to implement logic gates. • Careful floorplanning and architecture definition [...]]]></description>
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		<title>what is LVS</title>
		<link>http://www.rficdesign.com/what-is-lvs</link>
		<comments>http://www.rficdesign.com/what-is-lvs#comments</comments>
		<pubDate>Fri, 25 Jan 2013 13:53:03 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5823</guid>
		<description><![CDATA[LVS verification is checking that the design is connected correctly. The schematic is the reference circuit and the layout is checked against it. In principle, the following is verified: • Electrical connectivity of all signals, including input, output, and power signals to their corresponding devices • Device sizes: transistor width and length, resistor sizes, capacitor [...]]]></description>
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		<title>Ground Bounce in pcb layout</title>
		<link>http://www.rficdesign.com/ground-bounce-in-pcb-layout</link>
		<comments>http://www.rficdesign.com/ground-bounce-in-pcb-layout#comments</comments>
		<pubDate>Sun, 13 Jan 2013 15:45:46 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[electronics]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5822</guid>
		<description><![CDATA[As digital devices become faster, their output switching times decrease. Faster switching times cause higher transient currents in outputs as they discharge load capacitances. These higher currents, which are generated when multiple outputs of a device switch simultaneously from a logic high to a logic low, can cause a board-level phenomenon known as Ground Bounce. [...]]]></description>
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		<title>Design Guidlines on PCB layout</title>
		<link>http://www.rficdesign.com/design-guidlines-on-pcb-layout</link>
		<comments>http://www.rficdesign.com/design-guidlines-on-pcb-layout#comments</comments>
		<pubDate>Sun, 13 Jan 2013 15:45:14 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[electronics]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5821</guid>
		<description><![CDATA[• Use multi-layer PCBs that provide separate VCC and ground planes. • Add 10 to 30 ohm resistors in series to each of the switching outputs to limit the current flow into each of the outputs. • Create synchronous designs that will not be affected by momentarily switching pins. • Assign I/O pins to minimize [...]]]></description>
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		<title>Advantage of using standard cells</title>
		<link>http://www.rficdesign.com/advantage-of-using-standard-cells</link>
		<comments>http://www.rficdesign.com/advantage-of-using-standard-cells#comments</comments>
		<pubDate>Sun, 13 Jan 2013 15:41:32 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5820</guid>
		<description><![CDATA[• Independent blocks became too big and complex for a full-custom design, so there was a need to speed up the circuit and layout design processes. • There was a shortage of specialized personnel capable of hand-crafting complex full-custom designed blocks; automation alleviated this problem. • Advances in the typical manufacturing process included increasing the [...]]]></description>
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		<title>What is ESD</title>
		<link>http://www.rficdesign.com/what-is-esd</link>
		<comments>http://www.rficdesign.com/what-is-esd#comments</comments>
		<pubDate>Sun, 13 Jan 2013 15:39:29 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5819</guid>
		<description><![CDATA[Electrostatic discharge is the discharge of a large amount of charge into a chip. This charge can be fatal to a chip because it may physically damage transistors that are hit with the charge, much like a structure that is hit by lightning. The magnitude of ESD can vary widely, but the duration of a [...]]]></description>
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		<title>CMOS Resistor Layout</title>
		<link>http://www.rficdesign.com/cmos-resistor-layout</link>
		<comments>http://www.rficdesign.com/cmos-resistor-layout#comments</comments>
		<pubDate>Sun, 13 Jan 2013 15:37:12 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[vlsi]]></category>

		<guid isPermaLink="false">http://www.rficdesign.com/?p=5818</guid>
		<description><![CDATA[considerations for the design of this resistor: • Choose the width and length of the resistor based on ESD requirements and performance characteristics. • Use more than one contact to connect a signal path that has the possibility of carrying high currents. • The width of the metal line should not be minimum and must [...]]]></description>
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