Analog layout

2 Responses to “Analog layout”

1. analog layout says:

   July 30, 2009 at 11:11 am

   Thanks for this analog and RFIC layout article ,
2. Guru says:

   January 11, 2010 at 2:59 pm

   IMPACT OF LAYOUT ON DEVICE AND CIRCUIT PERFORMANCE
   the details of device/mixed-mode simulations and effect of the position of the pocket on the device and circuit performance are discussed. The doping profiles for both LAC and conventional MOS transistors were generated using a standard ISE DIOS process simulator [22]. The process flow for LAC MOSFETs is identical to that of conventional MOSFETs except for the threshold adjust implant, which was done through a tilted angle implantation from the source side, after the gate electrode formation [8]. The channel implant (BF2) for conventional devices was carried out before the gate oxidation, while for the LAC devices, a tilted channel implant (BF2 at 7 ) was done after the gate electrode formation. This implant dose was adjusted to achieve identical threshold voltage for the two devices. The corresponding threshold voltages and channel doping are shown in Table I for all the devices. In this table, represents the channel doping for conventional devices, represents the peak pocket doping at the source end and represents the doping at the drain side in LAC devices. The existing process models were used for both the devices with the device parameters such as junction depth, effective gate length, and deep source/drain depths adjusted to be identical. ISE DESSIS device simulator was used for device simulations with the optimized model parameters tuned with the experimental characteristics using a 0.2- m fabricated device. Drift-diffusion models were used in device simulations for both the technologies. ISE mixed-mode simulator was used for the circuit simulations except for OPAMP simulations where the mixed-mode simulations become impractical due to large number of transistors.